/***************************************************************************************
* Copyright (c) 2014-2022 Zihao Yu, Nanjing University
*
* NEMU is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
*          http://license.coscl.org.cn/MulanPSL2
*
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
*
* See the Mulan PSL v2 for more details.
***************************************************************************************/

#ifndef __ISA_RISCV64_H__
#define __ISA_RISCV64_H__

#include <common.h>

typedef struct {
  word_t gpr[32];
  vaddr_t pc;
} riscv64_CPU_state;

// decode
typedef struct {
  union {
    uint32_t val;
  } inst;
} riscv64_ISADecodeInfo;

//CSRs
typedef struct {
  word_t mstatus;
  word_t mtvec;
  word_t mepc;
  word_t mip;
  word_t mie;

  union {
    word_t mcause; 
    struct {
      //TODO write the mcause bit info 
    };
  };
  
  
    
} CSR;

enum {
  MSTATUS_ADDR = 0x300,
  MTVEC_ADDR = 0x305,
  MEPC_ADDR = 0x341,
  MCAUSE_ADDR = 0x342,
  MIE_ADDR = 0x304,
  MIP_ADDR = 0x344,
};

enum {
  MCAUSE_INTR = 1ull << 63,
  MCAUSE_ECALL_M = 11|MCAUSE_INTR,
  MCAUSE_TIM_INT_M = 7|MCAUSE_INTR,
};

enum {
  MSATUS_MIE_MASK = 1 << 3,
  MSATUS_MPIE_MASK = 1 << 7,
  MSATUS_MPP_MASK = 3 << 11,
  MIE_MTIE_MASK = 1 << 7,
  MIP_MTIP_MASK = 1 << 7,
  MIP_MSIP_MASK = 1 << 3,
};

#define isa_mmu_check(vaddr, len, type) (MMU_DIRECT)

#endif
